As the process geometries for integrated circuits progress to ever smaller scales, design constraints on the components of those integrated circuits become ever more strict. In particular, in contemporary integrated circuit design, more and more physical phenomena related to the materials from which the integrated circuit are constructed must be taken into account.
For example, as the conduction elements of integrated circuits get smaller, the effects of electromigration must be considered. Electromigration is the process by which ions in the conduction elements are transported due to momentum transfer from conducting electrons. The smaller the dimensions of a conduction element, the more sensitive it is to the damaging effects of electromigration, resulting over time in the poor performance or even failure of that conduction element. Hence, in addition to the lower sizing limits on conduction elements imposed by the lithographic techniques used to produce integrated circuits, electromigration effects also impose a lower limit on the dimensions of such conduction elements.
For a given current to be conducted by a conducting element, an electromigration constraint can be defined. This electromigration constraint puts a lower limit on the width of that conducting element in dependence on the amount and type of current that will be carried by the conducting element. Some conducting elements, such as those directly connected to a voltage supply, will only carry current in one direction (sometimes called a ‘DC current’). Other conducting elements, such as those connected to the output of a logic cell, will carry current in two directions (sometimes referred to as a ‘RMS current’) as the output load of the cell is charged and discharged. Electromigration width constraints for conducting elements are typically significantly stricter for DC current carriers than for RMS current carriers, since the former are subjected to an uni-directional current flow, which acts more aggressively to relocate ions in the conduction elements.
However the choice of width of a conducting element is not without upper limits either. Parasitic capacitance effects increase with the increasing width of a conducting element and, more significantly, the width of the conducting elements in an integrated circuit are a factor in determining the overall size of the integrated circuit. Thus, as efforts are made to reduce the scale of integrated circuits ever further, upper limits on the width of conducting elements are also brought ever lower.
Accordingly it would be desirable to provide an improved technique for sizing the conduction elements of an standard cell used to produce an integrated circuit, which seeks to balance the above-described competing constraints.